Three-Dimensional Fin-Structured Semiconducting Carbon

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Three-Dimensional Fin-Structured Semiconducting Carbon Nanotube Network Transistor Dongil Lee,†,⊥ Byung-Hyun Lee,†,⊥ Jinsu Yoon,‡ Dae-Chul Ahn,† Jun-Young Park,† Jae Hur,† Myung-Su Kim,† Seung-Bae Jeon,† Min-Ho Kang,§ Kwanghee Kim,§ Meehyun Lim,∥ Sung-Jin Choi,*,‡ and Yang-Kyu Choi*,† †

School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea ‡ School of Electrical Engineering, Kookmin University, 77 Jeongneung-ro, Seongbuk-gu, Seoul 02707, Korea § Department of Nano-process, National Nanofab Center (NNFC), Daejeon 34141, Korea ∥ Test and Package Technology Group, Mechatronics R&D Center, Samsung Electronics, 1-1 Samsungjeonja-ro, Hwaseong-si, Gyeonggi-do 18448, Korea S Supporting Information *

ABSTRACT: Three-dimensional (3-D) fin-structured carbon nanotube field-effect transistors (CNT-FETs) with purified 99.9% semiconducting CNTs were demonstrated on a large scale 8 in. silicon wafer. The fabricated 3-D CNTFETs take advantage of the 3-D geometry and exhibit enhanced electrostatic gate controllability and superior charge transport. A trigated structure surrounding the randomly networked single-walled CNT channel was formed on a fin-like 3-D silicon frame, and as a result, the effective packing density increased to almost 600 CNTs/μm. Additionally, highly sensitive controllability of the threshold voltage (VTH) was achieved using a thin back gate oxide in the same silicon frame to control power consumption and enhance performance. Our results are expected to broaden the design margin of CNT-based circuit architectures for versatile applications. The proposed 3-D CNT-FETs can potentially provide a desirable alternative to silicon based nanoelectronics and a blueprint for furthering the practical use of emerging low-dimensional materials other than CNTs. KEYWORDS: carbon nanotubes, 3-D structure, fin field-effect transistor (FinFET), wafer-scale, high packing density materials.12−14 Therefore, the performance enhancement and energy efficiency of CNT-based FETs (CNT-FETs) have been carefully researched, and CNT-FETs have been identified as suitable for use in digital logic circuits.12,13,15−18 In particular, although the transfer process-induced defects in emerging materials, including 2-D materials, are problematic, CNTs are less sensitive to this issue. Therefore, CNT-FETs are more appropriate for wafer-scale fabrication than other 2-D materials.19 To date, notable approaches to enhance the performance of CNT-FETs have been reported, including decreasing the channel length to below 10 nm, using a gate-all-around structure or achieving size-independent contact resistance, demonstrating that the potential of CNT-FETs exceeds that of

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ver the past several decades, Moore’s law has driven the performance enhancement of the integrated circuit and has guided the scaling of silicon transistors. However, because of the aggressive downsizing of metal-oxidesemiconductor field-effect transistors (MOSFETs), further extending Moore’s law encounters critical problems, such as physical limitations and short-channel effects (SCEs), affecting the fabrication process and performance.1,2 To overcome these challenges, transistors based on novel materials have emerged.3−5 Thus, various low-dimensional materials, such as carbon nanotubes (CNTs), graphene, and other two-dimensional (2-D) materials, have recently become highly attractive as “beyond silicon” materials.6−11 Among these, single-walled CNTs have been reported to be attractive for further downscaling. CNT technology has been predicted to exceed the performance requirements suggested by the International Technology Roadmap for Semiconductors by a factor of up to 2−3 at the 11 nm node, in contrast to other emerging © 2016 American Chemical Society

Received: August 12, 2016 Accepted: November 10, 2016 Published: November 10, 2016 10894

DOI: 10.1021/acsnano.6b05429 ACS Nano 2016, 10, 10894−10900

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ACS Nano silicon.20−22 However, achieving higher-level purity and increasing the packing density of semiconducting CNTs remain the primary main challenges to improve these materials’ practicality. To satisfy the demand for higher-purity semiconducting CNTs, some groups have employed CNTs with purities exceeding 99%. 23−27 In accordance with such approaches, semiconducting enriched CNT solution-processed devices with 99.9% purity were demonstrated in our previous work, showing the feasibility using these materials to achieve low power consumption.28,29 However, regarding increasing the packing density, the conventional limitcommonly considered to be ∼125 CNTs/μmwas surpassed using various techniques, such as ion-exchange chemistry,30 solution shearing,31 Langmuir−Blodgett,32 and Langmuir−Schaefer techniques.33 Although these techniques have produced CNT densities of approximately 500 CNTs/μm under ideal conditions, combining good scalability and facile process availability with high density, which is required for the waferscale manufacturing of CNT-based nanoelectronics, remains challenging. In particular, the structural engineering of CNTs with increased packing density is more challenging than material engineering to exploit a desired electrical property.33 In this regard, the structural innovation of a fin field-effect transistor (FinFET), a type of three-dimensional (3-D) gated vertical structure that represents an advancement beyond 2-D gated planar silicon channel-based devices (MOSFETs) can serve as a guide for the structural engineering of CNT-FETbased devices.34 In the historical evolution of silicon channelbased MOSFETs, the 3-D gated structure was the driving force underlying the extension of Moore’s law, resulting in enhanced performance, improved productivity, reduced fabrication costs, and decreased power consumption.35,36 Considering the significance of CNTs with higher packing densities for the feasibility of high-performance CNT-FETs, using this 3-D gated structure can be an effective approach to advance beyond Moore’s law, similar to the Si-FinFET with the 3-D gated structure. Furthermore, to realize a CNT-FET with improved purity and density, the process compatibility with complementary MOS (CMOS) fabrication would lead to synergy via the fusion of the CNT material and the silicon process-based optimal structure.37,38 In this work, 3-D fin-structured CNT-FETs with purified 99.9% semiconducting CNTs fabricated based on the combination of a silicon-CMOS compatible process and a typical solution process are demonstrated on an 8 in. Si wafer. The fabricated CNT-FETs are based on a trigated structure surrounding the CNT channel formed on a fin-like 3-D silicon frame employing three channel faces, thereby improving the electrical performance because of the enhanced electrostatic gate controllability and superior charge transport. Moreover, given the fin-structured 3-D silicon frame, the effective packing density of the randomly networked CNTs can be increased to nearly 600 CNTs/μm in the same footprint layout area. These features prove that silicon process-based structural optimization is effective for achieving densely packed CNT channels on a wafer-scale substrate. The highly reproducible silicon process also permitted the fabrication of 3-D CNT-FETs with various dimensions. For example, the channel length (LCH) and fin width (WFIN) can be varied easily by photolithography, and the fin height (HFIN) is controlled by the etching time of the 3-D silicon frame. A 2-D planar-type CNT-FET was also fabricated as a control device. Compared to the previous report, which was based solely on simulated data of the 3-D CNT-FET, our

fabricated 3-D CNT-FET exhibited acceptable electrical performances: on/off current ratio (ION/IOFF) above 105, a steep subthreshold swing (SS) of 85 mV/dec, and a current density of 3.9 μA/μm.37 Additionally, highly sensitive controllability of the threshold voltage (VTH) was achieved by incorporating a thin back gate oxide (BGO) in the same structure. The dummy fin-structured 3-D silicon frame not only provides mechanical support for the CNTs but also plays the role of the back gate. This tunable VTH, even in the 3-D CNTFETs, is highly advantageous for customization by end-users via the enhancement and modulation of the performance. Thus, our work provides a pathway toward the feasible nanofabrication-based mass production of emerging materials other than silicon.

RESULTS AND DISCUSSION The overall schematic of the 3-D fin-structured CNT-FET is shown in Figure 1a, and the cross-sectional high-resolution

Figure 1. Details of the 3-D CNT-FET, including the formation of a fabricated device. (a) Schematic illustration of the 3-D CNT-FETs on a bulk silicon substrate. The entire process is fully compatible with the silicon-based CMOS process. (b) Cross-sectional TEM image along the A−A′ direction. The 3-D CNT fin structure consists of CNTs and dielectric layers surrounding the silicon and silicon oxide fin structure. (c) TEM image of the CNT on the channel area with a diameter of